General IC Design Concepts

• What is IC design?
  IC design is the process of creating the layout, schematic, and functionality of an integrated circuit, which is a set of electronic circuits on a small semiconductor material, typically silicon.

• What are the two main phases of IC design?
  The two main phases are front-end design (logic and circuit design) and back-end design (physical design, including layout and verification).

• What is the difference between analog and digital IC design?
  Analog IC design deals with continuous signals and focuses on amplifiers, oscillators, etc., while digital IC design deals with discrete signals and focuses on logic gates, flip-flops, etc.

• What is a schematic in IC design?
  A schematic is a diagram that represents the electrical connections and components of an IC using standardized symbols.

• What is a layout in IC design?
  A layout is the physical representation of an IC, showing the geometric arrangement of components and interconnects on the semiconductor substrate.

Schematic Design

• What tools are commonly used to create schematics?
  Tools like Cadence Virtuoso, Synopsys Custom Compiler, and Mentor Graphics are commonly used.

• What is a netlist?
  A netlist is a text-based description of the connections between components in a schematic, used as an input for simulation or layout.

• Why is hierarchy used in schematic design?
  Hierarchy organizes complex designs into manageable blocks, improving readability and reusability.

• What is a symbol in a schematic?
  A symbol is a graphical representation of a component (e.g., transistor, resistor) used in the schematic editor.

• How do you simulate a schematic?
  Schematics are simulated using tools like SPICE, where inputs are applied, and outputs are analyzed for functionality and performance.

Layout Design

• What is the purpose of a layout in IC design?
  The layout translates the schematic into a physical design that can be fabricated on a chip.

• What is a polygon in IC layout?
  A polygon is a shape used to define regions like metal layers, diffusion areas, or polysilicon in the layout.

• What is a standard cell in layout design?
  A standard cell is a pre-designed layout of a logic gate (e.g., AND, OR) used in digital IC design.

• What is the role of metal layers in a layout?
  Metal layers provide interconnects between components, routing signals and power across the chip.

• What is a via in IC layout?
  A via is a vertical connection between different metal layers in the layout.

• What is the purpose of a guard ring in layout?
  A guard ring is a structure around sensitive areas (e.g., analog circuits) to reduce noise and latch-up.

• What is the difference between a full-custom and semi-custom layout?
  Full-custom layout involves manual design of all components, while semi-custom uses pre-designed cells (e.g., standard cells) for efficiency.

• What is a dummy structure in layout?
  Dummy structures are added to ensure uniformity in fabrication processes, like CMP (Chemical Mechanical Polishing).

• Why is symmetry important in analog layout?
  Symmetry reduces mismatch and parasitic effects, improving performance in analog circuits.

• What is a DRC-clean layout?
  A DRC-clean layout is one that passes all Design Rule Checks, ensuring it meets fabrication requirements.

Design Rule Checking (DRC)

• What is DRC in IC design?
  DRC (Design Rule Checking) verifies that a layout adheres to the fabrication process rules, such as minimum spacing or width.

• What is a DRC error?
  A DRC error occurs when a layout violates a design rule, such as insufficient spacing between metal lines.

• What is the minimum width rule in DRC?
  The minimum width rule specifies the smallest allowable width for a feature (e.g., metal or poly) in the layout.

• What is the spacing rule in DRC?
  The spacing rule defines the minimum distance required between two adjacent features in the layout.

• Why are DRC rules process-specific?
  DRC rules depend on the fabrication technology (e.g., 7nm, 65nm), as each process has unique limitations.

• What tools are used for DRC?
  Tools like Calibre (Mentor Graphics), IC Validator (Synopsys), and Virtuoso DRC are commonly used.

• What is a soft DRC error?
  A soft DRC error is a warning that doesn’t prevent fabrication but may affect yield or performance.

• What is a hard DRC error?
  A hard DRC error is a violation that must be fixed, as it prevents successful fabrication.

• What is a density rule in DRC?
  A density rule ensures uniform material distribution (e.g., metal or poly) across the chip to avoid fabrication issues.

• How do you fix a DRC violation?
  Adjust the layout by increasing spacing, resizing features, or rerouting connections to meet the rules.

Layout vs. Schematic (LVS)

• What is LVS in IC design?
  LVS (Layout vs. Schematic) is a verification step that ensures the layout matches the schematic in terms of connectivity and components.

• What does LVS check for?
  LVS checks for netlist equivalence, missing components, and incorrect connections between layout and schematic.

• What is a net mismatch in LVS?
  A net mismatch occurs when the connections in the layout don’t match those in the schematic.

• What is a device mismatch in LVS?
  A device mismatch happens when a component (e.g., transistor) in the layout differs from the schematic in type or size.

• What tools are used for LVS?
  Tools like Calibre LVS, Assura (Cadence), and PVS (Synopsys) are used for LVS checks.

• What is an LVS-clean design?
  An LVS-clean design means the layout and schematic are fully consistent with no errors.

• What is a short circuit in LVS?
  A short circuit is an unintended connection between two nets detected during LVS.

• What is an open circuit in LVS?
  An open circuit is a missing connection in the layout that should exist per the schematic.

• Why is LVS run after DRC?
  DRC ensures the layout is manufacturable, while LVS ensures it matches the intended design, so DRC comes first.

• What is a parasitic extraction in LVS?
  Parasitic extraction identifies unintended capacitances and resistances in the layout, often run alongside LVS.

Parasitic Effects and Post-Layout Simulation

• What are parasitic effects in IC design?
  Parasitic effects are unintended capacitances, resistances, and inductances introduced by the layout.

• How do parasitics affect circuit performance?
  Parasitics can slow down signals, increase power consumption, or cause timing issues.

• What is parasitic extraction?
  Parasitic extraction is the process of calculating parasitic elements from the layout for simulation.

• What is a post-layout simulation?
  Post-layout simulation tests the circuit’s performance including parasitic effects extracted from the layout.

• What is RC extraction?
  RC extraction calculates the resistance (R) and capacitance (C) of interconnects in the layout.

• Why is post-layout simulation slower than pre-layout?
  Post-layout simulation includes detailed parasitic data, increasing computational complexity.

• What is a back-annotation?
  Back-annotation updates the schematic or netlist with parasitic data from the layout.

• What is a critical path in post-layout simulation?
  The critical path is the longest delay path in a circuit, often affected by parasitics.

• How do you reduce parasitic capacitance?
  Increase spacing between metal lines or use lower dielectric materials.

• What is a lumped model in parasitic extraction?
  A lumped model simplifies parasitics into a single equivalent R, C, or L value for simulation.

Advanced Layout Techniques

• What is double patterning in layout?
  Double patterning splits a dense layout into two masks to achieve smaller feature sizes in advanced nodes.

• What is a finFET in IC layout?
  A finFET is a 3D transistor structure used in modern nodes (e.g., 7nm) for better control and performance.

• What is electromigration in layout design?
  Electromigration is the movement of metal atoms due to high current density, potentially causing failures.

• How do you mitigate electromigration?
  Use wider metal lines, add vias, or use materials like copper instead of aluminum.

• What is antenna effect in layout?
  The antenna effect is charge buildup on metal during fabrication, which can damage gates.

• How do you fix the antenna effect?
  Add antenna diodes or break long metal lines with vias to higher layers.

• What is a tap cell in layout?
  A tap cell connects the substrate or well to a power supply to prevent latch-up.

• What is a decap cell in layout?
  A decap (decoupling capacitor) cell reduces power supply noise by storing charge locally.

• What is clock tree synthesis in layout?
  Clock tree synthesis designs a balanced network to distribute clock signals with minimal skew.

• What is power gating in layout?
  Power gating uses switches to turn off unused circuit blocks, reducing power consumption.

Fabrication and Process Technology

• What is a process node in IC design?
  A process node (e.g., 7nm, 14nm) refers to the technology size of transistors and features in fabrication.

• What is a mask in IC fabrication?
  A mask is a patterned template used in photolithography to define features on the wafer.

• What is CMP in IC fabrication?
  CMP (Chemical Mechanical Polishing) planarizes the wafer surface during fabrication.

• What is a foundry in IC design?
  A foundry is a company (e.g., TSMC, GlobalFoundries) that manufactures ICs based on designer layouts.

• What is a PDK in IC design?
  A PDK (Process Design Kit) is a set of files provided by the foundry, including rules, models, and libraries.

• What is a GDSII file?
  GDSII is a file format containing the final layout data sent to the foundry for fabrication.

• What is tape-out in IC design?
  Tape-out is the final step of sending the completed design (GDSII) to the foundry for manufacturing.

• What is a reticle in IC fabrication?
  A reticle is a single mask pattern used to expose a portion of the wafer during lithography.

• What is DFM in IC design?
  DFM (Design for Manufacturability) optimizes the layout to improve yield and reliability in fabrication.

• What is yield in IC fabrication?
  Yield is the percentage of functional chips produced from a wafer.

Miscellaneous IC Design Topics

• What is a latch-up in IC design?
  Latch-up is a parasitic short circuit in CMOS caused by unintended thyristor activation.

• How do you prevent latch-up?
  Use guard rings, substrate taps, and proper spacing between n- and p-wells.

• What is ESD protection in IC design?
  ESD (Electrostatic Discharge) protection uses circuits like diodes to safeguard the chip from static damage.

• What is a PLL in IC design?
  A PLL (Phase-Locked Loop) is a circuit that synchronizes an output clock with a reference clock.

• What is a bandgap reference in IC design?
  A bandgap reference generates a stable voltage independent of temperature and supply variations.

• What is a current mirror in IC design?
  A current mirror is a circuit that copies a reference current to other parts of the design.

• What is matching in analog layout?
  Matching ensures identical performance of paired devices (e.g., transistors) by minimizing layout differences.

• What is a differential pair in IC design?
  A differential pair is a circuit used in amplifiers to process two input signals symmetrically.

• What is noise in IC design?
  Noise is unwanted electrical interference that degrades signal quality.

• How do you reduce noise in layout?
  Use shielding, guard rings, and separate analog/digital power supplies.

Practical and Debugging Questions

• What happens if DRC fails?
  The layout cannot be fabricated correctly, leading to potential shorts, opens, or yield loss.

• What happens if LVS fails?
  The chip may not function as intended due to mismatches between the design and layout.

• How do you debug a DRC error?
  Identify the violation in the DRC report, locate it in the layout, and adjust the design accordingly.

• How do you debug an LVS error?
  Compare the schematic and layout netlists to find discrepancies in connections or components.

• What is a floating net in LVS?
  A floating net is a connection in the layout or schematic that isn’t tied to any node.

• What is a marker in DRC/LVS tools?
  A marker highlights the location of an error in the layout for easier debugging.

• Why does a layout pass DRC but fail LVS?
  DRC checks physical rules, while LVS checks functional equivalence, so connectivity issues may persist.

• What is a black box in LVS?
  A black box is a placeholder for a missing or incomplete subcircuit during verification.

• How do you handle large layouts?
  Use hierarchical design and divide the layout into smaller, manageable blocks.

• What is a timing violation in digital IC design?
  A timing violation occurs when a signal doesn’t meet setup or hold time requirements.

Advanced and Emerging Topics

• What is 3D IC design?
  3D IC design stacks multiple layers of circuits vertically to save space and improve performance.

• What is a TSV in 3D ICs?
  A TSV (Through-Silicon Via) is a vertical connection through the silicon substrate in 3D ICs.

• What is EUV lithography?
  EUV (Extreme Ultraviolet) lithography uses short-wavelength light to pattern smaller features in advanced nodes.

• What is quantum IC design?
  Quantum IC design involves creating circuits for quantum computing, using qubits instead of classical bits.

• What is an SoC in IC design?
  An SoC (System on Chip) integrates multiple subsystems (e.g., CPU, memory) into a single IC.

• What is an IP block in IC design?
  An IP (Intellectual Property) block is a reusable design module (e.g., USB controller) licensed for use in an IC.

• What is machine learning in IC design?
  Machine learning optimizes tasks like placement, routing, and DRC in modern IC design flows.

• What is a photonic IC?
  A photonic IC uses light (photons) instead of electrons for data transmission, often for high-speed applications.

• What is a mixed-signal IC?
  A mixed-signal IC combines analog and digital circuits on the same chip, like ADCs or DACs.

• What is the future of IC design?
  The future includes smaller nodes (e.g., 3nm), 3D integration, quantum computing, and AI-driven design automation.

PDK

• What is included in a PDK?
  A PDK includes design rules, SPICE models, layout libraries, DRC/LVS rule decks, and parasitic extraction files.

• Why is a PDK important in IC design?
  A PDK ensures that the design is compatible with the foundry’s fabrication process, reducing errors and improving yield.

• What is a SPICE model in a PDK?
  A SPICE model provides electrical characteristics of components (e.g., transistors) for circuit simulation.

• What is a technology file in a PDK?
  A technology file contains process-specific information like layer definitions, via stacks, and design constraints.

• What is a rule deck in a PDK?
  A rule deck is a set of files used by DRC and LVS tools to verify that the layout adheres to process rules.

• What is a process corner in a PDK?
  A process corner represents variations in fabrication parameters (e.g., fast, slow, typical) for simulation.

• What is a Monte Carlo simulation in a PDK?
  Monte Carlo simulation analyzes the impact of process variations on circuit performance using statistical methods.

• What is a library in a PDK?
  A library includes pre-designed cells (e.g., standard cells, IO cells) and their layouts, schematics, and models.

• What is a foundry-certified PDK?
  A foundry-certified PDK is validated by the foundry to ensure accuracy and compatibility with their process.

• How do you update a PDK?
  Download the latest version from the foundry, verify compatibility with existing designs, and integrate it into the design environment.